How are computer chips made so small?

A computer chip is packed with tiny switches called transistors, and the newest have billions. Nvidia’s flagship AI chip, Rubin, has 336 billion of them. To fit that many, the gates of neighbouring transistors sit about 45 to 50 nanometres apart. A human hair is about 80,000.

This guide follows the HanaHow episode, which draws on Dwarkesh Patel’s podcast tour of Intel’s factories, What will computer chips look like in 2045? (22 October 2026), with Intel’s Chris Auth and Kevin Fischer. It covers how small a transistor is, what it does, why shrinking made transistors leak, how their design changed to stop it, how the newest ones are built, how the patterns are printed with light, and what happens in the factory when something goes wrong.

How small a transistor is

A nanometre (nm) is a millionth of a millimetre. Chips like the newest iPhone’s are sold as 2 nanometres: Apple says the iPhone 18 Pro’s A20 Pro chip is “Built using the latest 2-nanometer process technology”. But that number doesn’t measure anything on the chip. It’s a name for a generation of chipmaking.

Intel said in 2021 that the industry’s naming “stopped matching the actual gate-length metric in 1997”. Paolo Gargini, an Intel veteran who led the industry’s technology roadmap, told IEEE Spectrum in 2020 that the number had lost its meaning, because “it had nothing to do with any dimension that you can find on the die”.

The real distances are much bigger. Centre to centre, neighbouring transistor gates sit 50 nm apart on Intel’s 18A process and 45 nm apart on TSMC’s N3, a distance chipmakers call the contacted gate pitch. The most tightly packed wires above them are 23 to 32 nm apart. That’s still small enough to fit about 1,600 to 1,800 gate spacings across a hair.

The slider goes from a hair down to the atoms a chip is made of, with how many of each would fit side by side across one.

Every step on the slider, counted against an 80,000 nm hair:

Step	Size	Across a hair
A human hair	about 80,000 nm	1
A drop of tin in an EUV machine	about 25,000 nm	about 3
A red blood cell	7,000 to 8,000 nm	about 10 to 11
An E. coli bacterium’s width	about 1,000 nm	about 80
Deep ultraviolet light, used before EUV	193 nm	about 410
The Covid virus	about 100 nm	about 800
Transistor gate spacing	45 to 50 nm	about 1,600 to 1,800
The tightest wire spacing	23 to 32 nm	about 2,500 to 3,500
Extreme ultraviolet (EUV) light	13.5 nm	about 5,900
“2 nm”	a name, not a size	none to count
Neighbouring silicon atoms	about 0.24 nm apart	about 340,000

Hairs vary: the US Environmental Protection Agency puts the average at about 70,000 nm, and the US National Nanotechnology Initiative at 80,000 to 100,000. The silicon spacing is worked out from NIST’s measurement of the cube of atoms that repeats through a silicon crystal, 0.543 nm along each side. Neighbouring atoms sit a quarter of the way along its longest diagonal, about 0.235 nm apart, so a single 50 nm gate spacing is more than 200 atom spacings wide.

How many transistors

• Nvidia Rubin: 336 billion transistors, Nvidia says. It’s Nvidia’s flagship AI chip.
• Nvidia Blackwell, the generation before: 208 billion, on two pieces of silicon joined into one chip.
• Apple M4, from 2024: 28 billion. Apple hasn’t given a count for its newer M5 and M6 chips or the iPhone 18 Pro’s A20 Pro.

What a transistor does

A transistor is a switch with no moving parts. Electrons flow from one end, the source, to the other, the drain. Between them, on top, sits the gate.

Put a positive voltage on the gate and it pulls electrons in the silicon underneath up towards it. A thin layer of insulation stops them reaching the gate, so they gather just below it and form a thin path from the source to the drain, called the channel. Current flows. Take the voltage away and the electrons spread out, the channel disappears and the current stops. On or off: a one or a zero.

Everything a chip works out is done by switches like this turning each other on and off.

Why shrinking made them leak

For decades, making transistors smaller made them better. Chris Auth, who leads development of the processes Intel has in manufacturing, says of the 1980s and 1990s: “We just made things smaller, transistors got faster, they got more reliable, and it was a very predictable cadence.” By the 2000s, “That’s not good enough anymore.”

As transistors shrank, the source and the drain got so close together that current leaked through even when the switch was meant to be off. A switch that leaks wastes power as heat, all the time, in every one of those billions.

The way out was a gate that reaches round more of the channel, so it holds it more firmly. That meant rebuilding the transistor.

Flat, then fins, then gate-all-around

Flat

On the old flat, or planar, transistor, the gate sits on the channel and only touches it from the top. Patel dates this design to 1960.

Fins, from 2011

A fin transistor stands the channel up as a thin wall of silicon. The gate drapes over it, so it grips the channel on three sides.

Hitachi researchers, among them Digh Hisamoto, built the first one in a lab in 1989 and called it DELTA. The name FinFET came from Chenming Hu’s group at the University of California, Berkeley, by 1999, in work Hisamoto co-wrote. Intel disclosed its own version in 2002 and called it a Tri-Gate transistor.

Intel announced its fin transistors on 4 May 2011. It said it was the first time “since the invention of silicon transistors over 50 years ago” that transistors with a three-dimensional structure would be “put into high-volume manufacturing”, and it started volume production on its 22 nm process later that year. The first chips, Intel’s third-generation Core processors, went on sale in April 2012.

Gate-all-around, from 2022

Gate-all-around slices the channel into thin ribbons, stacked one above another, and the gate wraps all the way round each one: top, sides and bottom.

Samsung was first to make chips this way, starting initial production on its 3 nm process on 30 June 2022. It calls its version MBCFET, Intel calls its own RibbonFET and TSMC calls them nanosheets. Intel’s 18A has been in production since 2025, and TSMC started volume production of its N2 at the end of 2025. Intel’s 18A also feeds power to the transistors from the back of the wafer, which leaves more room for the signal wires on top.

Auth on the step after fins: “Well, gate-all-around’s really the ultimate transistor out there.”

Why it took so long

Transistors with the gate wrapped round the channel go back to at least 1988, when Toshiba researchers made what they called a surrounding gate transistor: an upright pillar of silicon with the gate around it. In 1990, J.P. Colinge and colleagues built a flat-lying version, closer to today’s ribbons, and called it a gate-all-around device.

So a version of gate-all-around was built a year before the first fin. It took another 34 years to reach the chips that do the computing, 11 years after fins did. Memory chips got there first: the cells in 3D NAND flash memory, which Samsung started mass producing in 2013, wrap their gate round an upright channel.

Auth says the idea was known in the 1990s, “But we knew there were going to be these problems on how you put this into high-volume manufacturing.” Engineers had other ways to improve transistors first, such as strained silicon, metal gates and fins, and “you don’t want to tackle something before you have to.” When they did take it on, it needed new materials and new tools, which chipmakers have to ask the equipment makers to invent. “I need a gas that can deposit this particular material,” as Auth puts it.

How the floating ribbons are built

You can’t carve a ribbon that floats in mid-air. So you build a sandwich, then take out the filling.

1. Stack the layers. Engineers grow alternating layers of silicon and silicon-germanium, over and over. IBM’s researchers call it a superlattice, a layered crystal of the two. Silicon-germanium makes a good filling because silicon can grow on it as one continuous crystal, and because it can be dissolved later without touching the silicon.
2. Add a dummy gate. The stack is cut into narrow strips and a dummy gate goes across them. It’s a stand-in. Later steps bake the wafer at around 1,000°C, and the materials of the real gate wouldn’t survive.
3. Grow the source and drain. On either side of the dummy gate, the source and drain are grown as small crystals, a process called epitaxy.
4. Take out the filling. Once the hot steps are done, the dummy gate is removed, and a chemical that, in IBM’s words, “selectively etches silicon germanium but does nothing to silicon” dissolves the silicon-germanium. The silicon ribbons are left hanging like tiny bridges between the source and the drain.
5. Put in the real gate. The gaps get an insulating coat a few atoms thick, a “high-k” material such as hafnium dioxide that lets the gate pull harder on the channel. Then the gate metal fills in around every ribbon. Both go on by atomic layer deposition, which builds a film up a layer of atoms at a time.

Building the gate last isn’t new. Intel’s engineers described it in IEEE Spectrum in 2007, when they first brought in high-k insulators and metal gates: putting the gate down “after the source and drain are formed” gets around the heat.

Printing with light

The ribbons’ thickness is set by how thick the layers are grown. The pattern for every layer, the outline of every transistor and every wire, is printed with light. It’s called lithography, and each layer goes round the same loop:

1. The wafer is coated in a resist, a layer that changes where light hits it.
2. Light shines through a mask, a stencil of the pattern (in EUV machines it bounces off one instead), and the machine shrinks the image down. ASML’s standard EUV machines shrink it four times.
3. The parts the light hit wash away. Some resists work the other way round.
4. What’s underneath is etched, or filled with new material, and polished flat.
5. The next layer goes on top.

A chip goes round that loop dozens of times. Connecting the transistors alone takes “more than a dozen layers of metal wire stacked above the transistors”, Patel says in the episode.

Shorter light, smaller patterns

“The shorter the wavelength, the finer the features that a single exposure can print,” as Patel puts it. So chipmaking light has kept getting shorter. ASML’s own history of its machines:

Light	Wavelength	Smallest features, ASML says
Mercury lamp, blue	436 nm	1,000 nm
Mercury lamp, ultraviolet	365 nm	220 nm
Krypton fluoride laser, deep ultraviolet	248 nm	80 nm
Argon fluoride laser, deep ultraviolet	193 nm	38 nm
Extreme ultraviolet	13.5 nm	13 nm, or 8 nm on the High-NA version

EUV

The finest layers use extreme ultraviolet light, at 13.5 nanometres, more than 14 times shorter than the 193 nm light before it. It’s hard to make and hard to handle.

Making it. Inside the machine, drops of molten tin about 25 micrometres across, roughly a third of the width of a hair, shoot out of a generator at 70 metres a second. A weak laser pulse flattens each one into a pancake, then a more powerful pulse vaporises it into a plasma that gives off EUV light. ASML says it does this 50,000 times a second. So a laser blasts 50,000 drops of molten tin a second. A normal way to make light.

Moving it. “EUV light is absorbed by everything, even air,” ASML says. So the whole path, from the tin to the wafer, is in a high vacuum, and instead of going through lenses, the light bounces off a series of mirrors, each built from many thin layers. The mask is a mirror too: it reflects the pattern rather than letting light through.

Who makes it. One company makes these machines: ASML, in the Netherlands. Reuters says they cost around $250 million each, and are “the size of a school bus and weighing 150 tons”. ASML’s annual report counts 48 EUV machines sold in 2025. Its newest High-NA version focuses a wider cone of light to print features about 1.7 times smaller, and Reuters puts its price at about $400 million.

Two or more passes. Even EUV can’t print the most crowded patterns in one go. Chipmakers split them across passes, each printing part of the pattern: “two, three, or even four passes”, Patel says. Each extra pass takes more time on the machine and is another chance for a defect.

Intel came to EUV later than TSMC. When it planned its 10 nm process, Auth says, “the conclusion was EUV was not ready”. Patel says TSMC put EUV into volume manufacturing in 2019, and Intel’s first EUV process reached products in 2023.

The factory

About 2,000 steps. Intel’s next chipmaking process, 14A, has “about 2,000 steps in the factory”, Auth says, each fine-tuned so it “can run thousands of wafers a week” and give the same result every time. Counts depend on what you count: a 2021 report from the Semiconductor Industry Association and Boston Consulting Group gave 400 to 1,400 steps, depending on the product.

About three months, often more. The same report put the average time to make a finished wafer at about 12 weeks, and up to 14 to 20 weeks for advanced processes. Much of that is waiting for the next machine. Critical Manufacturing, which makes factory software, says the biggest contributor to that time “is typically waiting time rather than actual processing time”.

The fast lane. Urgent experiments can jump the queue. Kevin Fischer’s job is deciding what goes on Intel’s newest production line, and Patel sat in on one of Intel’s Hot Topics meetings, where those calls get made, this one about improving 18A and 18A-P. Fischer says the factory has “a tiered system of what we call hot boxes”. The top grade, HotBox 1, “gets priority at every single tool”. He compares it to a carpool lane: “Everyone clear out of that lane except for that one experiment, and that one experiment races down the highway.”

Every other wafer waits, and the people running the factory are not fans. “If you had a factory person in here, they don’t like playing that card,” Fischer says, “because you end up using the tools inefficiently so that you can go super fast.”

Finding what went wrong

Intel finds defects two ways, Auth says. Inspection tools look at the wafers as they go through, and at the end, the chips are tested to see which ones fail. Then a failing chip is sliced open and the cut edge, called a cross-section, goes under a transmission electron microscope. From that, in Auth’s words, “you’ll be able to say, ‘Oh, that defect is between these layers, so it must have come from this section of the flow.’” Which layer it’s in tells you which step went wrong.

One problem in the meeting Patel sat in on was epi nodules, lumps on the source and drain crystals. “During the deposition of our epitaxy, we get abnormal growth, a little thing like a tumor. It’s growing super fast,” Fischer says. “That causes problems, because one epi will short to the wrong epi and you get transistors not working.” The engineers were looking at a special clean to get rid of the nodules, and at what was causing them, working on several fixes at once. “Sometimes it’s not the one you expect first.”

Then they change that step, and run the wafers again.

Sources

• Dwarkesh Patel: What will computer chips look like in 2045?, Dwarkesh Podcast, 22 October 2026, with Intel’s Chris Auth and Kevin Fischer. The quotes from Intel’s engineers and from Patel are from its official transcript.
• Transistor counts: Nvidia on Rubin and Blackwell, and Apple on the M4.
• Node names and real sizes: Apple on the iPhone 18 Pro, Intel’s statement of 26 July 2021, IEEE Spectrum’s A Better Way to Measure Progress in Semiconductors, Intel’s VLSI Symposium release of 16 June 2026, SemiWiki on TSMC’s 3 nm papers at IEDM 2022 and Tom’s Hardware on Intel’s 18A paper at VLSI 2025.
• The slider’s other sizes: the US EPA’s particulate matter basics, the US National Nanotechnology Initiative’s Just How Small Is “Nano”?, Ron Milo and Rob Phillips’s Cell Biology by the Numbers on human cells, E. coli and viruses, Bar-On, Flamholz, Phillips and Milo’s SARS-CoV-2 (COVID-19) by the numbers (eLife, 2020) and NIST’s lattice parameter of silicon (CODATA 2022).
• Transistor history: Hisamoto, Kaga, Kawamoto and Takeda, DELTA (IEDM 1989), the Semiconductor History Museum of Japan on FinFETs, Intel’s 3-D transistor announcement of 4 May 2011 and 10-Q for the third quarter of 2011, TechPowerUp on Ivy Bridge going on sale, Takato and colleagues’ surrounding gate transistor (IEDM 1988), Colinge and colleagues’ gate-all-around device (IEDM 1990), Samsung on 3 nm gate-all-around production and 3D vertical NAND, imec on 3D NAND and TSMC on N2.
• Building the ribbons: Ye, Ernst and Khare of IBM, The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore’s Law (IEEE Spectrum, 2019), Semiconductor Engineering on stacked nanosheets and Bohr, Chau, Ghani and Mistry of Intel, The High-k Solution (IEEE Spectrum, 2007).
• Lithography and EUV: ASML on EUV lithography systems and light and lasers, ASML’s 2025 annual report, Reuters on the $250 million ASML printer (28 January 2026) and TrendForce on High-NA’s price.
• The factory: the Semiconductor Industry Association and BCG, Strengthening the Global Semiconductor Supply Chain in an Uncertain Era (April 2021), and Critical Manufacturing on cycle times in chip factories.